The present invention relates to a timer circuit, and more particularly to a watchdog timer circuit suited for use in a microcomputer to detect abnormal program execution such as abnormal termination of the program and infinite-loop operation.
In an information processing equipment such as a microcomputer, there sometimes occurs a program abnormal termination or an operation within an infinite loop. In order to detect such abnormal program execution, a watchdog time circuit is employed.
A prior art watchdog time circuit is constituted by a counter having a reset function and counting a clock signal. This counter is reset cyclically by a program. The reset operation of the counter by the program is carried out within a time when the count value of the counter does not overflow. Accordingly, so long as the program is executed normally, the overflow signal is not obtained from the counter. On the other hand, when the program is abnormally executed, the counter is not reset, so that the counter produces the overflow signal. The overflow signal brings a program counter into an initial condition. The information processing equipment is thereby returned to a normal operation state.
However, the counter requires a large number of bits construction even in a microcomputer. For this reason, a semiconductor chip is made large in area and a large power is consumed in a one-chip microcomputer equipped with the prior art watchdog timer.